本帖最后由 冥界3大法王 于 2026-4-16 11:05 编辑
如何开发一款。。。可以自动的拆分 。。。 自动的投喂 和 自动的采食 解决当前困扰？
比如说吧：
https://wwaso.lanzouu.com/iQu5T3ndq7xg
样本为： X:\x64dbg\bin\mnemdb.json
如果上传到DeepSeek网页端，让它翻译只能翻译65%。。。于是问题来了。。。
如何制定规则。。。
- 按上限往下一点进行拆分 (比如上传文档好像最大50M，多少行有待考察） 所以此道命题拆成两份即可
- {。。。}, 保证每次拆分格式的段落存在【所以大小和容错可以自由一些】
- 自动上传下一个
- 自动的回收胜利果实并组装一起回填原始文档
当然了楼下肯定会说申请API KEY啊，你是大款你无敌，你牛X你有的是token啊。
token无穷注册机都能自动编出来（经实践测试确实是可以的）
可是俺们是穷人啊。所以。。。求思路：
 我说的意思大家明白了吧？ 加个老虎表情。
内容如下：
[Asm] 纯文本查看 复制代码 {
"__github_x86-64": "https://github.com/nologic/idaref/blob/master/x86-64.sql",
"__license_x86-64": "GPLv2",
"_github_x86-64-brief": "https://github.com/radareorg/radare2/blob/c4d416c7b96d2735c24a2f9e2787df3fdb764c71/libr/asm/d/x86.sdb.txt",
"_license_x86-64-brief": "GPLv3",
"x86-64": [
{
"description": "AAA-ASCII Adjust After Addition\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\n37 AAA NP Invalid Valid ASCII adjust AL after addition.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied\r\nsource and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD\r\ninstruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The\r\nAAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.\r\nIf the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there\r\nwas no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4\r\nthrough 7 of the AL register are set to 0.\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n IF ((AL AND 0FH) > 9) or (AF = 1)\r\n THEN\r\n AX <- AX + 106H;\r\n AF <- 1;\r\n CF <- 1;\r\n ELSE\r\n AF <- 0;\r\n CF <- 0;\r\n FI;\r\n AL <- AL AND 0FH;\r\nFI;\r\n\r\nFlags Affected\r\nThe AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF,\r\nSF, ZF, and PF flags are undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AAA"
},
{
"description": "AAD-ASCII Adjust AX Before Division\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\nD5 0A AAD NP Invalid Valid ASCII adjust AX before division.\r\nD5 ib AAD imm8 NP Invalid Valid Adjust AX before division to number base\r\n imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the\r\nAH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD\r\ninstruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the\r\nAX register by an unpacked BCD value.\r\nThe AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H.\r\nThe value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10)\r\nnumber in registers AH and AL.\r\nThe generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the\r\n\"Operation\" section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH\r\nfor decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust\r\nASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine\r\ncode (D5 imm8).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n tempAL <- AL;\r\n tempAH <- AH;\r\n AL <- (tempAL + (tempAH * imm8)) AND FFH;\r\n (* imm8 is set to 0AH for the AAD mnemonic.*)\r\n AH <- 0;\r\nFI;\r\nThe immediate value (imm8) is taken from the second byte of the instruction.\r\n\r\nFlags Affected\r\nThe SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AAD"
},
{
"description": "AAM-ASCII Adjust AX After Multiply\r\nOpcode Instruction Op/ 64-bit Compat/ Description\r\n En Mode Leg Mode\r\nD4 0A AAM NP Invalid Valid ASCII adjust AX after multiply.\r\nD4 ib AAM imm8 NP Invalid Valid Adjust AX after multiply to number base\r\n imm8.\r\n\r\n\r\n\r\n Instruction Operand Encoding\r\n Op/En Operand 1 Operand 2 Operand 3 Operand 4\r\n NP NA NA NA NA\r\n\r\nDescription\r\nAdjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD\r\nvalues. The AX register is the implied source and destination operand for this instruction. The AAM instruction is\r\nonly useful when it follows an MUL instruction that multiplies (binary multiplication) two unpacked BCD values and\r\nstores a word result in the AX register. The AAM instruction then adjusts the contents of the AX register to contain\r\nthe correct 2-digit unpacked (base 10) BCD result.\r\nThe generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked\r\ndigits of any number base (see the \"Operation\" section below). Here, the imm8 byte is set to the selected number\r\nbase (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted\r\nby all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the\r\ninstruction must be hand coded in machine code (D4 imm8).\r\nThis instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.\r\n\r\nOperation\r\nIF 64-Bit Mode\r\n THEN\r\n #UD;\r\n ELSE\r\n tempAL <- AL;\r\n AH <- tempAL / imm8; (* imm8 is set to 0AH for the AAM mnemonic *)\r\n AL <- tempAL MOD imm8;\r\nFI;\r\nThe immediate value (imm8) is taken from the second byte of the instruction.\r\n\r\nFlags Affected\r\nThe SF, ZF, and PF flags are set according to the resulting binary value in the AL register. The OF, AF, and CF flags\r\nare undefined.\r\n\r\nProtected Mode Exceptions\r\n#DE If an immediate value of 0 is used.\r\n#UD If the LOCK prefix is used.\r\n\r\nReal-Address Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\nVirtual-8086 Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n\r\n\r\n\r\n\r\nCompatibility Mode Exceptions\r\nSame exceptions as protected mode.\r\n\r\n64-Bit Mode Exceptions\r\n#UD If in 64-bit mode.\r\n\r\n\r\n\r\n\r\n",
"mnem": "AAM"
},
{
"描述": "set extended control register",
"mnem": "xsetbv"
},
{
"描述": "test if in transactional execution",
"mnem": "xtest"
}
]
}
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发表于 2026-4-16 10:46
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发表于 2026-4-16 17:33
